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- #TopLevelNode<BSVC>
-
- ------------------------------------------------------------------------------
- #Node<BSVC>
-
- BSVC is a microprocessor simulation framework written in C++ and Tcl/Tk.
- It was developed as a senior design project at North Carolina State University
- by Bradford W. Mott. BSVC provides a graphical user interface and a
- collection of C++ classes to facilitate the development of microprocessor
- simulators. So far the BSVC framework has been used to developed a
- Motorola 68000 simulator and a HECTOR 1600 simulator. The BSVC distribution
- contains the following:
-
- - BSVC Graphical User Interface (written in Tcl/Tk)
-
- - BSVC Simulator Framework (C++ classes)
-
- - #ToNode<Motorola 68000 simulator> & assembler
-
- - #ToNode<Hector 1600> simulator & assembler
-
- For more information point your WWW browser at the BSVC home page:
-
- http://www2.ncsu.edu/eos/service/ece/project/bsvc/www/
- #NodeEnd<BSVC>
-
- ------------------------------------------------------------------------------
- #Node<Motorola 68000 simulator>
-
- The Motorola 68000 simulator included in the BSVC distribution simulates the
- 68000 at the software level. This means the simulator does not understand
- what goes on in the 68000 at the hardware level. Instead the simulator
- performs a set of actions for each instruction that gives the same result.
-
- NOTES
-
- - Address and Bus errors do not generate a "complete" exception stack
- - Some illegal instructions may be mistaken for real instructions
- - Double bus errors cause the 68000 to halt and require a system reset
-
- DEVICES
-
- The 68000 simulator provides two devices that can be attached to the
- microprocessor. These devices are the M68681 Dual UART and RAM. For
- a complete description of these devices consult the BSVC User Manual.
- #NodeEnd<Motorola 68000 simulator>
-
- ------------------------------------------------------------------------------
- #Node<Hector 1600>
-
- The HECTOR 1600 is a 16-bit microprocessor built in a 4-month time-span by
- five graduate students and one faculty advisor at North Carolina State
- University. Due to the short design cycle and engineering inexperience,
- HECTOR was built as simply as possible. However, the simple design not only
- enabled the machine to be built by the required deadline, but also caused the
- instruction set to become orthogonal, powerful, and easy-to-use.
-
- If you have any questions about the HECTOR 1600 architecture contact:
-
- Dr. Thomas K. Miller
- tkm@eos.ncsu.edu
- #NodeEnd<Hector 1600>
-
-